1. Field of the Invention
The present invention relates to a decoding device receiving a coded succession of bits and delivering a decoded succession of bits, said coded succession being obtained by coding a succession of bits to be coded by converting each bit to be coded into two successive bits, a bit to be coded having one or other of two values which are associated, one with a single one of the pairs of different coded bits and the other alternately with one and other of the two pairs of identical coded bits, the decoding device comprising clock recovery means controlled by said coded succession and delivering a clock signal of a period equal to the duration of a pair of bits of said coded succession, and means for decoding the pairs, receiving said coded succession and said clock signal and delivering said decoded succession.
Coding of the above type, in which a bit to be coded of value 0 is converted into the pair of bits 01, for example, and a bit to be coded of value 1 is converted alternately into the pair 00 and into the pair 11 is usually called coded mark inversion or CMI coding.
The advantages of such coding are the spectral properties and the redundance of the coded signal, which facilitate transmission thereof as well as the detection of errors during this transmission.
2. Description of the Prior Art
A device of the above type is already known from the French Pat. No. 2 024 873. In this device the clock recovery means are such that the clock signal is set, with respect to the coded succession received, so that its rising fronts are in phase, or in phase opposition with the transitions between pairs of the coded succession. The factors which cause the clock signal to lock in phase or in phase opposition may be considered as random. The result is that there is one chance out of two that the decoding means, controlled by the clock signal, decodes the true pairs of bits of the coded signal and output a correct decoded signal. In the opposite case, the decoding means decode false pairs and the output signal is incorrect. To overcome this ambiguity, the decoding means of the above mentioned patent are adapted for detecting the unused pair of different coded bits, or prohibited pair, here the pair 10, and for acting on the clock recovery means so as to shift the clock signal by a half period should the prohibited pair be detected.
This device has, on the one hand, the drawback of requiring detection means adapted for detecting the prohibited pair and, on the other hand, the disadvantage of delivering an incorrect output signal as long as the prohibited pair has not been detected, in the case where the clock signal is badly locked at the outset.
The present invention aims at overcoming these drawbacks.